Update clock frequencies to match the infinity ergodox

This commit is contained in:
Kaleb Elwert 2017-01-09 11:15:10 -08:00
parent a702f4631e
commit 49a00a535f

View file

@ -29,21 +29,10 @@
/* PEE mode - 48MHz system clock driven by external crystal. */
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_PEE
#define KINETIS_PLLCLK_FREQUENCY 96000000UL
#define KINETIS_SYSCLK_FREQUENCY 48000000UL
#if 0
/* FEI mode - 48 MHz with internal 32.768 kHz crystal */
#define KINETIS_MCG_MODE KINETIS_MCG_MODE_FEI
#define KINETIS_MCG_FLL_DMX32 1 /* Fine-tune for 32.768 kHz */
#define KINETIS_MCG_FLL_DRS 1 /* 1464x FLL factor */
#define KINETIS_SYSCLK_FREQUENCY 47972352UL /* 32.768 kHz * 1464 (~48 MHz) */
#define KINETIS_CLKDIV1_OUTDIV1 1
#define KINETIS_CLKDIV1_OUTDIV2 1
#define KINETIS_CLKDIV1_OUTDIV4 2
#define KINETIS_BUSCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY
#define KINETIS_FLASHCLK_FREQUENCY KINETIS_SYSCLK_FREQUENCY/2
#endif
#define KINETIS_PLLCLK_FREQUENCY 72000000UL
#define KINETIS_SYSCLK_FREQUENCY 72000000UL
#define KINETIS_BUSCLK_FREQUENCY 36000000UL
#define KINETIS_FLASHCLK_FREQUENCY 24000000UL
/*
* SERIAL driver system settings.